This invention is in the field of voltage and current reference circuits as used in integrated circuits. Embodiments are directed to startup circuits for such reference circuits.
The powerful computational and operation functionality provided by modern integrated circuits has enabled the more widespread distribution of computing power in larger-scale systems. One example of such distributed electronic functionality is the so-called “Internet of Things” (IoT) contemplates the widespread deployment of electronic devices as sensors and controllers, with networked communications among those devices. Modern smartphones and wearables also deploy computational and operational functionality into a large number of distributed nodes; implantable medical devices constitute another type of distributed functionality. Many of these applications necessitate the use of batteries or energy scavenging devices to power the integrated circuits. As such, many modern integrated circuits are called upon to be “power-aware”, designed to consume minimal power during operation and standby.
Voltage and current reference circuits are important functions in a wide range of modern analog, digital, and mixed-signal integrated circuits, in order to optimize the performance of such circuits as operational amplifiers, comparators, analog-to-digital and digital-to-analog converters, oscillators, phase-locked loops and other clock circuits, and the like. This optimization is especially important for power-aware applications in which power consumption can be a dominating factor in circuit and system design. As well known in the art, voltage and current reference circuits ideally generate their reference levels in a manner that are stable over variations in process parameters, power supply voltage levels, and operating temperature (PVT).
FIG. 1a illustrates bias reference circuit 5, constructed in the conventional manner as well known in the art. This bias reference circuit 5 includes p-channel metal-oxide-semiconductor (PMOS) transistors 2ap, 2bp coupled in current mirror fashion, with their sources at the Vdd power supply and their gates coupled together at the drain of transistor 2ap. The drain of transistor 2ap is coupled to the drain of n-channel MOS (NMOS) transistor 2an, which has its source coupled to the Vss reference level through resistor 3. The gate of NMOS transistor 2an is coupled in current mirror fashion to the gate and drain of NMOS transistor 2bn, which has its source at Vss. These interconnected PMOS and NMOS current mirrors establish a self-bias loop, in which the PMOS current mirror enforces equality of the NMOS drain currents (assuming transistors 2ap and 2bp are of the same size), which renders the voltage Vgn at the gates of NMOS transistors 2an, 2bn, as well as the gate voltage at PMOS transistors 2ap, 2bp to be relatively independent of the Vdd voltage. The PMOS gate voltage can be applied to the gates of output PMOS transistors 4ap, 4bp to produce stable bias currents IBIASD1, IBIASD2, respectively, and the NMOS gate voltage Vgn can be applied to the gates of output NMOS transistors 4an, 4bn, 4cn to produce stable bias currents IBIASU1, IBIASU2, IBIASU3, respectively, as shown in FIG. 1a. 
FIG. 1b illustrates “bandgap” reference circuit 13, constructed in the conventional manner as another type of reference circuit known in the art. As in the case of bias reference circuit 5 of FIG. 1a, bandgap reference circuit 13 is also self-biased and thus not sensitive to the Vdd voltage; in addition, bandgap reference circuit 13 is additionally designed to be stable over temperature variations. This temperature stability derives from its output reference voltage being based on both a parameter that varies proportionally with temperature (proportional to absolute temperature, or PTAT) and also a parameter that is complementary to absolute temperature (CTAT). In the example of FIG. 1b, PMOS transistor 6p, with its source at Vdd, serves as a current source, with its gate controlled by the output of amplifier 15. The drain of PMOS transistor 6p is connected to two bipolar transistor legs through resistor 7. One leg is formed by resistor 9a connected between resistor 7 and the emitter of p-n-p transistor 8a; the other leg is formed by resistor 9b connected between resistor 7 and resistor 11, which in turn is connected to the emitter of p-n-p transistor 8b. The bases and collectors of transistors 8a, 8b are connected to the Vss reference level. P-n-p transistors 8a, 8b may be realized as parasitic devices in conventional CMOS processes, as is common in the art. In this conventional arrangement, the emitter of transistor 8a is connected to one input of amplifier 15, while the other input of amplifier 15 is connected to the node between resistors 9b and 11. In this way, the output voltage AMPOUT from amplifier 15 is based on a CTAT voltage (the base-emitter voltage of transistor 8a) and a PTAT voltage (the difference in the base-emitter voltages of transistors 8a, 8b, which is reflected as the voltage drop across resistor 11). In addition to providing the gate voltage of PMOS transistor 6p in a self-bias manner, this output voltage AMPOUT also sets the gate voltage of output PMOS transistors 10ap, 10bp, which produce reference currents IPTATD1, IPTATD2, respectively. Reference current IPTATD1 also serves as the bias current for amplifier 15. The drain of output PMOS transistor 10bp is connected to the drain of NMOS transistor 12n, which is connected in diode fashion. The resulting gate and drain voltage of transistor 12n also serves as the gate voltage of output NMOS transistors 14an, 14bn, which produce reference currents IPTATU1, IPTATU2, respectively.
Each of the well-known self-biased reference circuits shown in FIGS. 1a and 1b, as well as other conventional self-biased reference circuits, have two stable operating points, namely the zero current point (e.g., no current conducted by transistors 2ap, 2bp, 2an, 2bn of FIG. 1a) and a non-zero current point that is, of course, the desired operating point. Start-up circuits are typically added to these reference circuits to ensure power-up into the desired operating state.
FIG. 2a illustrates an example of a conventional “common-source” start-up circuit, as applied to bandgap reference circuit 13 of FIG. 1b (shown in part in FIG. 2a). In this example, start-up circuit 20 includes current source 21 and current source 23 connected in series between the Vdd power supply and the Vss reference level, and NMOS transistor 24 with its gate connected at a node between current sources 21 and 23. In this example, current source 21 conducts a current IBIASD1, and may be constituted by an output transistor of a reference circuit (e.g., by output transistor 4ap in bias reference circuit 5 of FIG. 1a) external to bandgap reference circuit 13 and thus not dependent on its start-up. Current source 23 conducts the current IPTATU1, and as such is constituted by an output transistor of bandgap reference circuit 13 itself, for example transistor 14an in the circuit of FIG. 1b. In this example, amplifier 15 of bandgap reference circuit 13 includes active load 22 at its output, as is typical in the art. In the conventional fashion, active load 22 is provided by a current mirror arrangement of PMOS transistors, with output node AMPOUT at the drain of the PMOS transistor in the mirror leg as shown in FIG. 2a. The drain of NMOS transistor 24 is connected to amplifier output node AMPOUT, and the source of transistor 24 is at Vss. As conventional, bandgap reference circuit 13 includes PMOS transistor 31 with its source and drain connected between the Vdd power supply voltage and node AMPOUT, and its gate receiving enable signal EN. PMOS transistor 31 thus serves to maintain node AMPOUT at Vdd when bandgap reference circuit 13 is not enabled (i.e., enable signal EN is at a low logic level), which keeps that node from floating and ensures that output transistors 6p, 10ap, 10bp are off; while bandgap reference circuit 13 is enabled by enable signal EN at a high logic level, PMOS transistor 31 is held off and does not affect the operation of the circuit. In operation, current IPTATU1 is initially zero, prior to the start-up of bandgap reference circuit 13. On the other hand, external current IBIASD1, which is present at start-up, pulls up the gate of transistor 24 toward the Vdd power supply voltage, turning on transistor 24 and pulling down node AMPOUT from its initial Vdd level (due to PMOS transistor 31 being on prior to enable) toward Vss. The low voltage at node AMPOUT turns on PMOS transistor 6p, which initializes conduction in transistors 8a, 8b of bandgap reference circuit 13 and ensures development of the desired reference voltages and currents. Once bandgap reference circuit 13 starts up as desired, current IPTATU1 at a level designed to overwhelm bias current IBIASD1, turning off transistor 24 and thus allowing amplifier 15 to control the generation of the various reference currents. In this manner, the current comparison between currents IPTATU1 and IBIASD1 at the gate of transistor 24 effectively implements a “handshaking” function between bandgap reference circuit 13 and start-up circuit 20, in that the current IPTATU1 that is generated by bandgap reference circuit 13 itself signals to start-up circuit 20 that it is to shut off.
While conventional start-up circuit 20 starts up bandgap reference circuit 13 at its desired operating point, it is quite sensitive to variations in the Vdd power supply voltage, as well as to process variations (i.e., variations in transistor parameters). In addition, NMOS transistor 24 is configured as a common-source amplifier in start-up circuit 20, which typically has a relatively high gain as known in the art. The high gain loop presented by this arrangement start-up circuit 20 is a significant source of instability in the overall bandgap reference circuit configuration.
FIG. 2b illustrates an example of another type of conventional start-up circuit known in the art as a “self-turn-off” start-up circuit. In this start-up circuit 20′, the amplifier output node AMPOUT is connected to the source of PMOS transistor 26, which has its drain connected to the Vss level through resistor 27. The gate of transistor 26 is coupled to the Vdd voltage via diode-connected PMOS transistor 28, and is pulled down by external current IBIASU1, such as may be generated by a bias reference circuit (e.g., circuit 5 of FIG. 1a). As in the circuit of FIG. 2a, PMOS transistor 31 holds node AMPOUT at the Vdd voltage prior to enabling of the circuit, ensuring startup from a known state upon enable signal EN turning off transistor 31. In operation at power-up, diode-connected PMOS transistor 28 will conduct reference current IBIASU1, which places its gate and drain voltage at a threshold voltage below the Vdd voltage (i.e., Vdd−Vt). This voltage Vdd−Vt also appears at the gate of transistor 26, while node AMPOUT is initially at a full Vdd voltage due to PMOS transistor 31 having been on prior to the enabling of the circuit. As a result, the gate-to-source voltage at transistor 26 is at its threshold voltage Vt, which turns on transistor 26 to conduct current to Vss through resistor 27, pulling down node AMPOUT at the drain of transistor 29 and the gate of transistor 6p toward Vss. Transistor 6p turns on accordingly, initiating the operation of the bandgap reference circuit. As the voltage at node AMPOUT is pulled down, transistor 26 turns off (its gate being clamped to Vdd−Vt), which effectively isolates start-up circuit 20′ from affecting the operation of bandgap reference circuit 13.
This conventional self-turn-off start-up circuit 20′ also has several limitations, particularly as used in modern power-aware integrated circuits. A first limitation is that no “handshaking” between start-up circuit 20′ and the reference circuit that it is starting up. This absence of handshaking control can result in significant power consumption if start-up circuit 20′ is slow or has failed. In addition, process variations in the manufacture of these conventional start-up circuits 20, 20′ can result in the output of amplifier 15 at node AMPOUT being driven fully to Vss, which requires a significant amount of charge (i.e., energy) before settling at the desired operating node. Because limiting of power consumption is critical in many power-aware systems, especially those in which “energy harvesting” is used to provide system power from a capacitor, this conventional start-up circuit 20′ is not favored for those applications.